Verification Engineer

Responsibilities

• Assist in developing and executing verification plans for digital and mixed-signal ASIC designs
• Support the creation of testbenches and test cases using SystemVerilog and UVM
• Run simulations and perform debugging to identify and resolve design issues
• Collaborate with design and verification teams to understand specifications and contribute to verification strategies
• Document verification results and contribute to coverage analysis and regression testing
• Learn and apply best practices in design verification and contribute to process improvements

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline
• 2-5 years of relevant experience in design or mixed-signal verification
• Strong understanding of digital logic design
• Familiarity with HDL languages such as SystemVerilog, Verilog, or VHDL
• Knowledge of SystemVerilog and UVM methodology
• Experience with Linux-based development environments and Git version control
• Excellent analytical and problem-solving skills

Preferred Qualifications

• Exposure to scripting languages such as Python, Perl, or Tcl
• Internship or academic project experience in ASIC/FPGA design or verification

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose to make our lives easier. As a leading expert in embedded processing, we provide scalable and comprehensive semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a diverse team of over 21,000 professionals globally, we design sustainable, power-efficient solutions that help people and communities thrive.