UVM Verification Engineer, Principal Engineer

Responsibilities

• Develop detailed verification testplans and comprehensive functional coverage models for complex memory interface IP
• Implement scalable UVM testbench infrastructure and design robust test cases to verify training firmware functionality on RTL PHY models
• Collaborate with architecture and implementation teams through technical reviews to ensure project alignment
• Diagnose and resolve complex verification and debugging challenges using advanced tools and methodologies
• Interpret standard and functional specifications to develop success path, corner case, and negative test scenarios
• Research and integrate emerging technologies in virtual prototyping and emulation to enhance verification efficiency
• Mentor junior engineers and contribute to team knowledge sharing and leadership development

Requirements

• Proficiency in SystemVerilog and UVM with hands-on experience in simulation and waveform debugging
• Expertise in assertion-based verification and coverage analysis techniques
• Bachelor’s degree or higher in Electrical or Computer Engineering, Computer Science, or a related field
• Experience with scripting languages for regression and build systems (Python, Perl, or Shell)
• Familiarity with Linux development environments and collaborative engineering workflows

Preferred Qualifications

• Knowledge of virtual prototyping, emulation, and C/C++ software/hardware co-simulation
• Understanding of LPDDR or other memory interface standards

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is a global leader in chip design, verification, and IP integration. Our technology is central to the Era of Pervasive Intelligence, driving innovation in industries ranging from self-driving cars to machine learning.