THW Client Co-op

Responsibilities

• Perform digital ASIC design and verification of Client sub-systems and cores within the ASIC IP team
• Implement and verify digital designs using SystemVerilog and UVM
• Conduct RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA-based validation
• Contribute to the development of client protocol mapping IP for Wavelogic coherent engine Chipsets
• Work collaboratively with design and verification engineers on well-defined tasks to broaden knowledge in optical networking

Requirements

• Currently enrolled in a Bachelor’s degree program in Electrical Engineering or Computer Engineering with good academic standing
• Previous experience with ASIC or FPGA development
• Proficiency with SystemVerilog, Verilog, VHDL, and Python
• Strong verbal and technical writing skills
• Ability to work independently and as part of a team environment

Preferred Qualifications

• Knowledge of OTN, Ethernet, and other Optical Networking standards
• Strong problem-solving and debugging skills
• Experience working in a Linux environment

Benefits

• Competitive hourly pay range ($27.00 - $37.50)
• Access to the Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation pay as required by applicable laws

About the Company

Ciena is a global leader in high-speed connectivity, committed to a people-first approach. We are a technology company that leads with humanity, driving business priorities alongside meaningful social, community, and societal impact.