Technologist, Mask Design Engineering

Responsibilities

• Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains.
• Ensure adherence to design specifications, performance requirements, and foundry rules.
• Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification.
• Execute parasitic extraction and sign-off methodologies to guarantee design integrity.
• Implement full-chip power distribution strategies and floorplanning optimization to minimize parasitics and reduce die size.
• Collaborate with design and process engineering teams across multiple sites to resolve issues and align methodologies.

Requirements

• 14+ years of proven expertise in custom full-chip IC Layout Design.
• Deep experience across Analog, Digital, and Mixed-signal domains.
• Proficiency with industry-standard layout verification tools (DRC/LVS, parasitic extraction).
• Strong background in floorplanning strategies and placement optimization.
• Proven ability to work with multi-site, cross-disciplinary teams.
• Excellent verbal and written communication skills.

Preferred Qualifications

• Knowledge of layout automation techniques.
• Experience managing small teams to drive project success.
• Proactive mindset toward continuous improvement and design efficiency.

About the Company

Sandisk relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions are the beating heart of the digital world. We combine powerhouse manufacturing capabilities with an industry-leading portfolio of products recognized globally for innovation, performance, and quality.