Technologist, ASIC Development Engineering (STA, Sign-Off)

Responsibilities

• Lead a team of STA engineers and take complete ownership of ASIC timing signoff.
• Architect and define organization-wide STA methodology, standards, and signoff frameworks.
• Collaborate with IP and Design teams on timing constraints development and review.
• Develop and implement advanced STA strategies to meet requirements for complex IC designs.
• Partner with cross-functional teams including design, verification, physical design, and DFT.
• Conduct thorough timing analysis, identify critical paths, and mitigate timing violations.
• Stay current with industry trends and incorporate emerging technologies into the team workflow.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 13 years of experience in Static Timing Analysis.
• Proven leadership experience managing and developing STA engineering teams.
• Demonstrated track record of timing signoff ownership on multiple successful tape-outs.
• Expert-level knowledge of industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.
• Deep understanding of MMMC, OCV, AOCV, POCV, SI analysis, and power-aware timing.
• Proficiency in scripting languages including TCL, Python, or Perl.
• Experience with advanced process nodes (e.g., 5nm, 3nm) is highly desirable.

About the Company

Sandisk relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions are the beating heart of the digital world. We combine powerhouse manufacturing capabilities with an industry-leading portfolio of products recognized globally for innovation, performance, and quality.