Technical Staff Engineer – Verification

Responsibilities

• Develop and maintain UVM/System Verilog based verification environments and Formal Tool based verification environments
• Define test plans, implement constrained-random and directed tests, develop assertions, and drive coverage closure
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve bugs
• Analyze code and functional coverage metrics to ensure comprehensive verification closure
• Work with product development teams to integrate the UVM test bench and tests at the SoC level
• Collaborate with Architect, Design, and applications groups to verify products and IP requirements
• Continuously improve verification methodology, reuse, and efficiency

Requirements

• Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering
• Minimum 8 years of experience in ASIC/SoC functional verification
• Hands-on experience with SystemVerilog language, assertions, and UVM methodology
• Hands-on experience developing IP-level and SoC-level verification environments
• Strong understanding of Digital Design, RTL fundamentals, and simulation/debug flows
• Excellent analytical, debugging, communication, and problem-solving skills

About the Company

Microchip Technology Inc. is a leading semiconductor company that provides solutions for various industries worldwide. With a team of over 17,000 members, we focus on empowering innovation to enhance the human experience through a culture of trust, empowerment, and diversity.