Static Timing Analysis (STA) Engineer

Responsibilities

• Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing signoff support
• Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams
• Assist in developing and validating timing constraints to ensure accurate modeling of design intent
• Work closely with design, architecture, and implementation teams to improve timing convergence
• Apply established STA methodologies and contribute to flow improvements and automation
• Support optimization efforts for performance, power, and area (PPA) through timing-driven analysis

Requirements

• 6+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs
• Solid understanding of STA fundamentals including setup/hold, timing paths, clocking, and CDC basics
• Experience with industry-standard tools such as PrimeTime or equivalent
• Familiarity with synthesis and place & route flows
• Working knowledge of RTL design using Verilog or SystemVerilog
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Preferred Qualifications

• Experience with FPGA architectures and timing flows
• Familiarity with advanced process nodes or high-speed designs
• Scripting experience in Tcl or Python for automation
• Exposure to large-scale or distributed engineering environments

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.