Staff Verification AE

Responsibilities

• Drive customer deployments of VCS/Verdi simulation and debug technology.
• Diagnose and troubleshoot complex technical issues in verification flows.
• Collaborate with global domain experts to gather requirements and contribute to the product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS/Verdi advantages and supporting benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface with customers, product validation, and R&D teams to propose implementation and validation improvements.
• Develop and optimize scripts using Perl, TCL, Python, or Shell to enhance workflow automation.

Requirements

• Bachelor's degree in Electronics with 5+ years of experience, or a Master's degree in Electronics with 3+ years of experience.
• Proficiency in verification technologies including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages such as Verilog, VHDL, and SystemVerilog.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills in Perl, TCL, Make, Shell, or Python.
• Working knowledge of UNIX environments.

Preferred Qualifications

• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, or Verdi.
• Exposure to GenAI technologies.

About the Company

Synopsys is a global leader in electronic design automation (EDA), providing the tools and technologies that enable the world's most advanced semiconductor designs.