Staff Engineer, Physical Design

Responsibilities

• Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, and power integrity
• Collaborate with SoC-level physical design teams on clocking strategies and floorplanning intent
• Apply clocking methodologies to ensure subsystem-level clock domains integrate into the broader SoC architecture
• Develop and scale subsystem closure methodologies, flows, and automation
• Mentor and guide physical design engineers within subsystem teams
• Work cross-functionally with RTL design, STA, power, verification, and backend teams
• Identify and mitigate physical design risks in coordination with SoC teams

Requirements

• 5+ years of experience in physical design for complex hierarchical SoCs
• Expertise in timing closure, constraint management, and congestion resolution
• Experience with power integrity and power-aware physical implementation
• Understanding of SoC-level floorplanning and clocking methodologies (clock tree architecture, skew management, clock gating)
• Hands-on experience with Synopsys ICC2, Fusion Compiler, PrimeTime or Cadence Innovus, Tempus, Certus
• Proficiency in Tcl, Python, or Perl scripting
• B.Tech or M.Tech in Electronics, Electrical Engineering, Computer Science, or related field

About the Company

Renesas is a leading global semiconductor company providing product solutions in the automotive, industrial, infrastructure, and IoT markets. With over 21,000 employees worldwide, we strive to make every endpoint intelligent through our robust portfolio of MCUs, SoCs, and analog products.