Staff Engineer, Design Enablement

Responsibilities

• Develop and define Physical Design methodologies to meet advanced SOC, MCU, and IP level objectives across all geometry nodes (3/5/16/22nm).
• Manage requirements and define tools and flows for Place & Route, UPF, Formal Verification, Floorplan, and Power-Plan.
• Partner with EDA vendors to proactively review, evaluate, and benchmark the latest tool and flow offerings in Physical Implementation domains.
• Collaborate with EDA vendors to review and resolve blocking issues.
• Act as a change agent for deploying new tools and methodologies across the organization.

Requirements

• 6-10 years of hands-on experience in Physical Design, including UPF, Formal & Physical verification, floorplan, power-plan, and Place & Route.
• Proven experience in delivering physical implementation closure methodology ensuring timing and physical convergence.
• Proficiency with Synopsys and Cadence tool sets (e.g., Fusion Compiler, Innovus).
• Strong scripting skills for automation and flow development using PERL, TCL, or Python.
• Bachelor, Master, or Ph.D. in Electronics Engineering with a specialization in the VLSI domain.

Preferred Qualifications

• Experience customizing flows and methodologies to meet low power and area objectives for SoCs/MCUs.
• Experience working with low geometry node issues and resolving complex blocking issues with EDA teams.

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose "To Make Our Lives Easier." As a leading expert in embedded processing, Renesas provides scalable and comprehensive semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a diverse team of over 21,000 professionals globally, we design sustainable, power-efficient solutions that help people and communities thrive.