Staff Engineer, ASIC/VLSI Synthesis and Design at Marvell - ScoutJobs - The AI-curated global job board
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Marvell
Posted 9 days ago

Staff Engineer, ASIC/VLSI Synthesis and Design

MarvellStaff Engineer, ASIC/VLSI Synthesis and Design

Requirements

Bachelor's or Master's/PhD in CS or EE, 3-5 years professional experience, ASIC implementation and synthesis experience, RTL to GDSII design flow knowledge, Synthesis and STA methodologies, Tcl, Perl, or Python proficiency, Advanced technology nodes (TSMC N4/N5) experience

Skills

ASICVLSIPythonTCL

About the role

Responsibilities

  • Develop and validate timing constraints for intricate SoC designs.
  • Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes for synthesis and sign-off flows.
  • Own front-end implementation tasks including Synthesis, UPF development, Logical Equivalence Checks (LEC), and Functional ECOs.
  • Analyze tradeoffs between power, performance, and area (PPA) to drive chip implementation.
  • Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
  • Automate front-end flows and processes using scripting languages such as Tcl or Python.
  • Ensure compliance with Netlist Handoff checklists for delivery to Physical Design.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3-5 years of professional experience (or Master’s/PhD with 2-3 years of experience).
  • Minimum of 1 year of industry experience specifically in ASIC implementation and synthesis.
  • Strong understanding of the full ASIC design flow from RTL to GDSII.
  • Hands-on experience with synthesis and STA methodologies.
  • Proficiency in synthesis tools, STA tools, and scripting languages (Tcl, Perl, or Python).
  • Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
  • Experience with functional ECOs and UPF development/validation.

Preferred Qualifications

  • Experience with Physical Aware Synthesis and industry-standard EDA tools.
  • Familiarity with physical design and timing optimization techniques to achieve timing closure.
  • Proven track record of delivering successful designs that meet strict PPA goals.

Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs.
  • Robust mental and physical health resources.
  • Recognition and service awards.

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, AI, and carrier architectures, our innovative technology is enabling new possibilities and fueling the transformative potential of tomorrow.

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Staff Engineer, ASIC/VLSI Synthesis and Design

Marvell · San Diego

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