Staff Engineer, ASIC Development Engineering (STA, Sign Off)

Responsibilities

• Own subsystem-level STA, providing direction and guidance to PnR teams for timing closure and synthesis report analysis
• Work with IP and Design teams on timing constraints development and review activities
• Develop and implement advanced STA methodologies and strategies to meet timing closure requirements for complex IC designs
• Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure optimal timing performance
• Drive the development and maintenance of STA scripts and tools to automate and streamline analysis processes
• Conduct thorough timing analysis, identify critical paths, and develop mitigation strategies for timing violations
• Prepare and present detailed timing reports and technical documentation to stakeholders

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Minimum of 5 years of experience in Static Timing Analysis (STA)
• In-depth knowledge of STA tools such as Synopsys PrimeTime or Cadence Tempus
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
• Proven track record of successfully executing STA for complex semiconductor designs

Preferred Qualifications

• Experience working with advanced process nodes such as 7nm or 5nm
• Proficiency with Constraints Manager and related automation tools

About the Company

Sandisk relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions are the beating heart of the digital world. We combine powerhouse manufacturing capabilities with an industry-leading portfolio of products recognized globally for innovation, performance, and quality.