Posted 11 days ago
Staff Engineer, ASIC Development Engineering
Sandisk
Requirements
ASIC verification expertise, System Verilog and UVM, Verilog, IP level verification, Testbench architecture development, Coverage closure, Gate level simulations, Serial protocols (UFS, PCIe, USB, MIPI), Memory protocols (AXI, PCIE, UFS, Flash), Python or Perl scripting, Bachelor of Engineering
Skills
SystemVerilogUVMVerilogPythonASIC
About the role
Responsibilities
- Define verification plans and independently create testbenches and testcases
- Lead IP level verification and testbench architecture development
- Develop testbench components and manage coverage closure (code and functional coverage)
- Perform gate level simulations to ensure design integrity
- Drive continuous process improvements to enhance quality and efficiency
Requirements
- 4-7 years of experience in ASIC verification
- Expertise in System Verilog, UVM, and Verilog
- Strong knowledge of serial protocols such as UFS, PCIe, USB, or MIPI
- Proficiency with memory protocols including AXI, PCIE, UFS, and Flash
- Experience with scripting languages like Python or Perl
- Bachelor of Engineering degree
About the Company
At Sandisk, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. We are a key partner to some of the largest and highest growth organizations in the world, providing the storage infrastructure that fuels a brighter, smarter future.
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Sandisk · Bangalore
