Staff Engineer, ASIC Development Engineering

Responsibilities

• Own subsystem-level Static Timing Analysis (STA), providing direction to PnR teams for timing closure and synthesis report analysis.
• Collaborate with IP and Design teams on timing constraints development and review activities.
• Develop and implement advanced STA methodologies and strategies to meet the requirements of complex IC designs.
• Partner with cross-functional teams, including design, verification, physical design, and DFT, to ensure optimal timing performance.
• Drive the development and maintenance of STA scripts and tools to automate and streamline analysis processes.
• Conduct thorough timing analysis to identify critical paths and develop mitigation strategies for timing violations.
• Prepare and present detailed technical documentation and timing reports to stakeholders.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5 years of experience in Static Timing Analysis (STA).
• Proven track record of successfully executing STA for complex semiconductor designs.
• In-depth knowledge of STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes.
• Excellent problem-solving, analytical, and communication skills.

Preferred Qualifications

• Experience working with advanced process nodes, specifically 7nm or 5nm.
• Proficiency with Constraints Manager and related automation tools.

About the Company

Sandisk is a global leader in Flash and advanced memory technologies. We relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. Our solutions serve as the beating heart of the digital world, driven by powerhouse manufacturing capabilities and an industry-leading portfolio recognized globally for innovation, performance, and quality.