Staff Engineer, ASIC Design Verification

Responsibilities

• Participate in verification strategy and methodology definitions
• Contribute to micro architecture specification and reviews
• Responsible for the verification of modules/subsystems of AI accelerators
• Architect test benches, create test plans, and implement test bench components in UVM
• Execute verification per plan to closure
• Work closely with architects and design engineers to define verification requirements and close functional and code coverage targets
• Provide support in post silicon bring up and debug

Requirements

• BE or MS in Computer/Electrical Engineering or Computer Science
• 10+ years of experience in ASIC verification
• Proficiency in UVM
• Strong language skills in C++ and SystemVerilog
• Experience in logic and SoC verification from planning to closure
• Understanding of verification flows and tools
• Experience in UCIe, HBM controller, or Memory DFT

Preferred Qualifications

• Experience in DDR and Custom HBM and related IP level or SOC level verification
• Knowledge of emerging technologies such as CXL, Computation in memory and storage, or AI LLM accelerators

About the Company

Samsung's DRAM Development Lab (DDL) focuses on developing new technology for memory and storage to solve key problems for Cloud and Data centers. The SOC team develops silicon solutions such as Custom HBM base die and AI accelerators.