Staff Engineer, ASIC Design/Implementation

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes for STA signoff.
• Perform static timing analysis (STA) using industry-standard tools such as PrimeTime.
• Own STA-related tasks including timing ECOs for blocks and SoCs, and developing custom scripts for histograms and flow management.
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct post-route timing checks and quality of results (QoR) analysis.
• Automate STA processes and flows using scripting languages like Tcl or Python.
• Create QoR dashboards and ensure compliance with timing signoff checklists and criteria.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3-5 years of professional experience, OR a Master’s/PhD with 2-3 years of experience.
• Minimum of 1 year of industry experience specifically in ASIC timing and STA.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Proficiency in STA tools and scripting languages such as Tcl, Python, or Perl.
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs and timing ECO creation.
• Proven track record of delivering successful designs that meet performance, power, and area goals.

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, AI, and carrier architectures, our innovative technology is enabling new possibilities and fueling the transformative potential of tomorrow.