Staff Design Verification Engineer

Responsibilities

• Architect and lead verification strategies for complex digital and mixed-signal designs
• Design and implement sophisticated UVM-based verification environments to ensure test coverage
• Provide technical mentorship to junior engineers and model professional behaviors
• Coordinate with design teams on verification requirements and sign-off criteria
• Lead complex debugging efforts across RTL and gate-level simulations
• Drive functional and code coverage closure using advanced methodologies
• Lead post-silicon validation activities to address critical issues
• Serve as a principal technical contact for key customers and industry partners

Requirements

• Expert-level knowledge of SystemVerilog and Universal Verification Methodology (UVM)
• Deep understanding of mixed-signal design principles and verification methodologies
• Extensive experience with EDA tools from Cadence or Synopsys
• Advanced proficiency in scripting languages such as Python, Perl, TCL, or Shell
• Proven ability to develop comprehensive verification plans and drive coverage closure
• Strong debugging skills across multiple design abstractions

Preferred Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field
• 7-10+ years of relevant digital design verification experience, specifically in mixed-signal environments

Benefits

• Competitive compensation and benefits package
• Opportunities for professional growth and continuous learning
• Collaborative and innovative work environment
• Work on cutting-edge projects with real-world impact

About the Company

Analog Devices, Inc. (ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. We combine analog, digital, AI, and software technologies to solve complex challenges in automation, robotics, healthcare, and energy.