Staff ASIC Design Verification Engineer

Responsibilities

• Verify ASIC RTL designs at both chip and block levels
• Define and track verification test plans
• Design and write constrained-random System Verilog testbenches using UVM (Universal Verification Methodology)
• Create and examine Functional Coverage and write System Verilog assertions
• Debug Firmware, RTL, and gate-level simulation failures
• Perform code coverage analysis and track bugs using tools like Jira

Requirements

• BSEE or MSEE degree
• Minimum of 2+ years of digital design or verification experience
• Proficiency in writing testcases using System Verilog and UVM
• Solid understanding of digital circuit design
• Experience debugging complex testbench and design-related issues
• Familiarity with scripting languages such as Python or Perl

Preferred Qualifications

• Experience working with High-Bandwidth Memory (HBM) products
• Strong organizational and communication skills for collaborating with design groups and customer support teams
• Ability to work independently and as part of a mixed-signal design team

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Retirement plans and competitive salary

About the Company

Synopsys is a leader in chip design, verification, and IP integration. We drive the innovations that shape the way we live and connect, providing the technology central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.