Staff ASIC Design Engineer

Responsibilities

• Design and implement RTL blocks with a focus on micro-architecture optimization
• Develop comprehensive micro-architecture specifications and technical documentation
• Execute synthesis, timing closure, and optimization activities
• Collaborate with firmware, software, design verification, FPGA, DFT, and backend teams
• Support prototyping, test program development, and chip validation
• Conduct design bring-up and debug on FPGA-based emulation platforms
• Implement and analyze assertions and coverage metrics
• Work with interface protocols including PCIe, USB, Ethernet, DDR, I2C/I3C, eSPI, and SPI
• Mentor junior engineers and provide technical guidance
• Utilize scripting languages and repository management tools to streamline workflows

Requirements

• 7+ years of experience in RTL logic design, verification, synthesis, and timing optimization
• Expertise in writing efficient, synthesizable RTL code in Verilog
• Strong SoC integration knowledge
• Proficiency in micro-architecture design
• Understanding of assertions, coverage analysis, and RTL synthesis methodologies
• Extensive experience with interface protocols (PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI)
• Experience with FPGA-based emulation platforms like HAPS or Veloce
• Fluency in Perl and Python for design automation
• Experience with Bitbucket, Jenkins, and JIRA
• Completion of at least one full tape-out cycle

Preferred Qualifications

• Silicon bring-up and debug experience on actual hardware
• Experience mentoring or leading junior design engineers
• Familiarity with industry design methodologies and standards

About the Company

Axiado is building the future of AI powered digital infrastructure, pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience, and real-time platform management.