STA Lead

Responsibilities

• Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners
• Own and drive timing signoff from synthesis through to final tapeout
• Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration
• Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths
• Drive MMMC timing methodology and ensure robust timing convergence across PVT corners
• Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization
• Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, and variation effects
• Lead timing ECO strategies and execute closure with minimal impact to power, area, and performance
• Collaborate with RTL and IP owners for timing budgeting and hierarchical timing signoff
• Mentor junior engineers and define best practices for timing methodology

Requirements

• 15+ years of hands-on experience in ASIC/SoC design implementation and timing closure
• Strong expertise in full-chip STA and timing signoff for large-scale SoCs
• Proven experience working with advanced technology nodes (7nm, 5nm, 3nm, or similar)
• Deep knowledge of synthesis, place-and-route, extraction, and signoff flows
• Solid understanding of clocking architecture, CDC implications, and timing exception handling
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or Computer Engineering
• Excellent communication, stakeholder management, and leadership skills

About the Company

AMD's mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we push the limits of innovation to solve the world’s most important challenges.