Sr Synthesis and Implementation Engineer

Responsibilities

• Perform logical and physical synthesis of RTL designs for digital blocks and sub-systems
• Develop and implement robust timing constraints (SDC) to achieve target frequencies
• Conduct STA, identify critical paths, and collaborate with design teams for timing closure
• Execute formal verification (LEC) to ensure functional equivalency between RTL and netlists
• Analyze and optimize power consumption and area to meet aggressive PPA requirements
• Collaborate with RTL designers, DFT engineers, and physical design engineers for seamless integration
• Develop and maintain automation scripts using Tcl, Python, or Perl for synthesis flows
• Evaluate and integrate new CAD tools and methodologies to improve design quality

Requirements

• Bachelor's or Master's degree in VLSI, Electronics Engineering, or a related field
• 5+ years of experience in digital ASIC/SoC design with a focus on synthesis and front-end implementation
• Proficiency with industry-standard synthesis tools such as Synopsys DC/FC or Cadence Genus
• Strong understanding of static timing analysis (STA) and tools like Synopsys PrimeTime or Cadence Tempus
• Experience with formal verification tools such as Synopsys Formality or Cadence Conformal
• Solid knowledge of Verilog/SystemVerilog and scripting languages (Tcl, Python, or Perl)
• Understanding of UPF, low-power design techniques, and power analysis concepts

Preferred Qualifications

• Experience with physical synthesis and floorplanning aspects
• Knowledge of DFT (Design for Testability) principles

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.