Sr. Staff R&D Engineer, Analog Design

Responsibilities

• Develop, debug, and maintain analog design flows based on extraction, simulation, and EMIR flows
• Support project-specific design environments for analog design circuit development across the global foundation IP R&D team
• Debug complex design issues spanning physical verification (DRC/LVS), extraction, simulation, and reliability analysis
• Build Python, TCL, and shell-based automation to eliminate manual steps and accelerate design cycles
• Configure and support IP project environments including Perforce data management and LSF job scheduling
• Collaborate directly with design teams to diagnose bottlenecks and deliver technical solutions

Requirements

• MSEE or BSEE degree with an emphasis on VLSI, Microelectronics, or Electronics Engineering
• 6+ years of hands-on experience in VLSI design, EDA tool development, or design flow engineering
• Proficiency in Python and scripting languages for automation
• Solid Linux/Unix knowledge and comfort working in command-line environments
• Deep knowledge of integrated analog circuit design fundamentals and the VLSI development lifecycle

Preferred Qualifications

• Experience with physical verification (DRC/LVS), extraction, simulation, or reliability analysis
• Experience with Cadence Virtuoso, UltraSim, or Synopsys tools such as ICV, StarRC, CustomCompiler, CustomSim, or Hspice

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.