Sr Staff Engineer (RTL Design & Verification)

Responsibilities

• Design and verify RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects
• Develop comprehensive test cases to ensure robust product functionality and performance
• Collaborate with customers and internal engineering teams to resolve technical issues through hands-on debugging and root cause analysis
• Contribute to the improvement of verification methodologies and automation flows
• Document design specifications, verification plans, and results to ensure transparency and repeatability
• Participate in code reviews and technical discussions to drive innovation

Requirements

• BS/MS in Computer Science, Electrical Engineering, or a related field
• 5+ years of hands-on experience in RTL design and verification
• Proficiency in Verilog, System Verilog, and EDA tools
• Strong skills in TCL scripting and Formal Verification methodologies
• Experience working in Unix/Linux environments
• Excellent written and verbal communication skills in English
• Strong debugging and problem-solving skills in complex chip design environments

Preferred Qualifications

• Knowledge of digital, analog, and mixed-signal IP/circuit design
• Familiarity with 3D-IC standards and semiconductor verification best practices

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is a leader in chip design, verification, and IP integration. We drive the innovations that shape the way we live and connect, providing the technology central to the Era of Pervasive Intelligence.