Sr Staff Engineer - Design Verification/VIP Verification Engineers at Synopsys - ScoutJobs - The AI-curated global job board
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Synopsys
Posted 10 hours ago

Sr Staff Engineer - Design Verification/VIP Verification Engineers

SynopsysSr Staff Engineer - Design Verification/VIP Verification Engineers

Requirements

Bachelor's or Master's in Electronics Engineering or Computer Science, 5+ years experience in Verification IP or SystemVerilog/UVM, Knowledge of AMBA, DFI, DRAM, PCIe, or Ethernet protocols, Proficiency in coverage-driven verification plans

Skills

SystemVerilogUVMPCIe

About the role

Responsibilities

  • Design, develop, and maintain Verification IP (VIP) using SystemVerilog and UVM for industry-standard protocols including DFI, DRAM, AMBA, PCIe, USB, and Ethernet
  • Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
  • Code sequences, test scenarios, and checkers to drive coverage-based verification across functional and code coverage dimensions
  • Debug complex simulation failures across multi-layer protocol stacks to identify root causes in both VIP logic and customer integration environments
  • Enhance existing VIP products for performance, reusability, and scalability as protocols evolve
  • Support customers during VIP integration and deployment, troubleshooting issues and ensuring successful bring-up
  • Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps

Requirements

  • Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
  • 5+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based test benches
  • Deep working knowledge of at least two industry-standard protocols such as AMBA (AXI, AHB, APB), DFI, DRAM, PCIe, or Ethernet
  • Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
  • Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis
  • Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries

Preferred Qualifications

  • Experience working directly with customers or field teams during product deployment

Benefits

  • Comprehensive medical and healthcare plans
  • Paid time away including ETO and FTO programs
  • Family support including maternity/paternity leave and adoption assistance
  • Employee Stock Purchase Plan (ESPP) with a 15% discount
  • Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across the semiconductor industry.

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Sr Staff Engineer - Design Verification/VIP Verification Engineers

Synopsys · Delhi

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