Sr Staff Design Verification Engineer

Responsibilities

• Define and own verification plans, methodologies, and coverage strategies for complex SoC designs
• Architect and implement verification environments from scratch and enhance existing frameworks
• Drive block-level, subsystem-level, and full-chip verification
• Build automation components including Agents, sequences, drivers, monitors, and scoreboards
• Integrate industry-standard VIPs and create custom transactors
• Lead end-to-end verification including Gate-level simulations, coverage analysis, regression, and triage
• Mentor junior and mid-level verification engineers
• Act as technical lead for key verification deliverables

Requirements

• Bachelor's degree in Electrical Engineering or equivalent practical experience
• 12+ years of experience with verification methodologies such as UVM
• Proficiency in Verilog, SystemVerilog (SV), C/C++, and Python
• Extensive experience with RTL and Gate-level simulation debugging
• Strong understanding of SoC architecture and mixed-signal designs
• Experience with industry-standard simulators, revision control, and regression systems
• Knowledge of analog components such as ADC, DAC, PLL, Oscillators, and PI controllers
• Experience with directed and constrained random verification methodologies

About the Company

Renesas is a leading global semiconductor company dedicated to making every endpoint intelligent. We provide innovative product solutions across the automotive, industrial, infrastructure, and IoT markets. With a diverse team of over 21,000 professionals worldwide, we strive to develop a safer, healthier, greener, and smarter world through our robust portfolio of MCUs, SoCs, Analog, and power products.