Sr. Manager, ASIC Verification - Interface IP- PCIe/CXL

Responsibilities

• Own the alignment between Verification IP (VIP) capabilities and Design IP verification needs, identifying gaps in feature coverage for both Controller and PHY.
• Drive requirements definition for VIP based on real Design IP verification use cases.
• Track PCI Express specification updates, ECNs, and errata, translating changes into actionable requirements.
• Review and critique testplans across projects to ensure best-in-class coverage and traceability.
• Report VIP deployment metrics and drive continuous improvement in integration flows.
• Work hands-on with UVM-based verification environments to validate VIP usage and model best practices.

Requirements

• 15+ years of hands-on experience in digital verification.
• Deep subject matter expertise in PCI Express Link Layer and PHY Layer, including specification details and errata.
• Proven experience in IP product development, specifically building Verification IP or deploying it for complex Design IP.
• Strong UVM knowledge and experience in UVM-based verification environments.
• Track record of driving results in cross-functional, matrixed organizations across different geographies.

Preferred Qualifications

• Experience with CXL or other coherent interconnect protocols.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.