Sr DFT Engineer

Responsibilities

• Define and implement DFT architecture for SoCs, including scan, MBIST, LBIST, and boundary scan
• Develop and integrate scan insertion, test compression, and ATPG patterns
• Implement memory BIST and logic BIST strategies
• Collaborate with RTL and physical design teams for DFT insertion and timing closure
• Perform DFT verification at RTL and gate-level simulations
• Work with ATE teams for test program development and silicon bring-up
• Optimize test coverage, pattern count, and test time

Requirements

• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, and JTAG
• Hands-on experience with industry standard ATPG tools
• Proficiency in UPF/CPF-based low-power DFT
• Knowledge of fault models such as stuck-at, transition, and path delay
• Familiarity with physical design constraints for DFT
• Experience in silicon debug and ATE bring-up
• Bachelor’s or Master’s degree in Electrical or Electronics Engineering

Preferred Qualifications

• Past experience with SoC level DFT
• Exposure to high-speed interfaces and DFT for mixed-signal blocks
• Strong problem-solving and communication skills

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.