Software Engineer – Performance Profiling

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. We are a fully in-person team in San Jose (Santana Row).

Responsibilities

• Lead the design and architecture of a comprehensive performance analysis suite, including data collection, processing pipelines, and user interfaces.
• Develop methods to capture performance data directly from custom ML accelerator hardware via driver interfaces.
• Implement tracing for host-side API calls and system-level events like CPU activity and PCIe traffic.
• Design techniques to correlate performance events across host CPU, device drivers, PCIe bus, and multiple accelerators.
• Build analysis modules to automatically identify performance limiters such as compute or memory bandwidth bottlenecks.
• Develop intuitive visualizations like timelines and resource utilization charts to communicate performance characteristics.
• Collaborate with hardware architects, firmware engineers, and compiler engineers to define tool requirements.

Requirements

• Strong proficiency in C++ or Rust
• Deep understanding of computer architecture (CPU, GPU, accelerators), memory hierarchies, and interconnects (PCIe)
• Proven experience in low-level performance analysis and profiling on complex hardware systems
• Experience with performance analysis tools such as NVIDIA Nsight, AMD uProf, Intel VTune, perf, or Tracy
• Experience working close to hardware, including reading performance counters or interacting with device drivers

Preferred Qualifications

• Proficiency in Python
• Direct experience developing performance analysis or debugging tools
• Experience with ML accelerator architectures (GPUs, TPUs, etc.)
• Kernel-mode driver development (Linux or Windows)
• Understanding of compiler internals and code optimization
• In-depth knowledge of the PCIe protocol and analysis tools
• Experience with multi-chip or multi-host accelerator systems
• Experience with firmware, embedded systems, or hardware description languages (Verilog, VHDL)