SoC Verification Engineer

Responsibilities

• Verify custom analog macros to ensure design correctness and reliability
• Partner with Design, Integration, and Test Engineering teams to define verification scope, develop strategies, implement test plans, and verify designs at the IP, cluster, and full-chip levels
• Collaborate with the CAD team to optimize and streamline our simulation flow
• Generate test patterns and support chip bring-up activities

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science
• 1-3 years of experience in DFT or digital design
• Strong debugging and analytical skills using RTL/gate-level design tracing tools (e.g., Verdi) and verification simulation tools (e.g., VCS)
• Familiarity with SoC fundamental architecture (clock, reset, power rail, I/O pad, package)

Preferred Qualifications

• Understanding of Design-for-Test methodologies including Scan, ATPG, BIST, and JTAG
• Proficiency in one or more scripting/programming languages: Python, Perl, Tcl, C, or C++
• Fluent English communication skills (written and verbal)