
Posted 22 days ago
SoC Timing (Static Timing Analysis/STA) Engineer, HBM
Micron
Requirements
10+ years chip-level STA experience, Experience with 5nm or below tape-outs, Expertise in Synopsys PrimeTime or Cadence Tempus, Proficiency in Python or Tcl scripting, Understanding of MMMC and OCV
Skills
PythonTCL
About the role
Responsibilities
- Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and environmental conditions
- Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, HBM interfaces, and DFT logic
- Drive timing closure at block, subsystem, and full-chip levels through critical path analysis and engineering change orders (ECOs)
- Perform multi-mode, multi-corner (MMMC) analysis, including clock domain crossing and on-chip variation (OCV, AOCV, POCV)
- Lead signal integrity and crosstalk analysis to identify and mitigate noise-induced timing issues
- Build and maintain STA automation and flows using Python and Tcl for reporting and regression tracking
- Conduct post-silicon timing correlation and define organization-wide STA methodologies and sign-off standards
- Mentor junior engineers and collaborate cross-functionally with RTL, Physical Design, and Verification teams
Requirements
- 10+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below
- Deep expertise with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus
- Expert understanding of advanced timing concepts including MMMC, on-chip variation, signal integrity, and power-aware timing
- Proven ability to develop and manage complex hierarchical SDC constraints for large systems on chip
- Proficiency in Python and/or Tcl scripting for timing flow automation and constraint management
Preferred Qualifications
- Experience with high-bandwidth memory (HBM), DRAM, or memory-centric SoC designs
- Exposure to design for test (DFT) timing, including scan, MBIST, and JTAG interfaces
- Experience with chiplet-based or 3D integrated circuit designs and die-to-die interface timing
- Familiarity with foundry process design kits, Liberty timing models, and advanced noise modeling
- Strong communication skills to present timing status and risks to senior leadership
Benefits
- Choice of medical, dental, and vision plans
- Income protection programs for illness or injury
- Paid family leave
- Robust paid time-off program and paid holidays
About the Company
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
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Micron · Richardson
