SOC Timing Analysis (STA) Engineer

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across all process corners, operating modes, and voltage/temperature conditions
• Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC) for clock domains, reset trees, HBM interfaces, and DFT logic
• Drive timing closure at block, subsystem, and full-chip levels through critical path analysis and timing engineering change orders (ECOs)
• Perform multi-mode, multi-corner (MMMC) timing analysis, including CDC timing and application of OCV, AOCV, and POCV derates
• Lead signal integrity and crosstalk analysis to identify and mitigate noise-induced timing violations
• Partner with RTL and architecture teams to provide early feedback on micro-architectural decisions and timing budgets
• Develop automation scripts in Python and Tcl for constraint generation, report extraction, and sign-off readiness reporting
• Perform post-silicon timing correlation by analyzing silicon measurement data against pre-silicon predictions

Requirements

• 10+ years of industry experience in chip-level static timing analysis with a track record of full timing sign-off on multiple tape-outs at 5nm or below
• Deep expertise with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus
• Expert-level understanding of advanced timing concepts, including MMMC, signal integrity, and power-aware timing in sub-5nm nodes
• Proven ability to develop complex SDC timing constraints for large hierarchical SoC designs
• Experience across the full RTL-to-GDS implementation flow, including synthesis, placement, CTS, and routing

Preferred Qualifications

• Exposure to design-for-test (DFT) concepts including scan, MBIST, and debug
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Familiarity with foundry process design kits, Liberty timing models, and advanced process variation modeling
• Strong analytical and debug skills to trace timing failures to root cause across RTL and physical implementation

Benefits

• Choice of medical, dental, and vision plans
• Income protection programs for illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.