SOC Engineering, Staff Engineer

Responsibilities

• Own and optimize the RTL-to-GDSII flow for UCIE IP, including floorplanning, place and route, timing closure, and signoff
• Integrate covercells, macros, and third-party IP blocks, ensuring clean abutment and proper power planning
• Automate tool flows using Tcl and Python to debug complex physical design issues and document best practices
• Collaborate with architecture, RTL, and circuit teams on test chip development to translate design intent into physical reality
• Prepare tape-out views, generate final documentation, and manage foundry design rule checklists through signoff

Requirements

• 5+ years of hands-on experience in block-level physical design
• Experience with advanced process nodes such as 7nm or below
• Deep working knowledge of floorplanning, place and route, timing closure, IR-drop, and electromigration analysis
• Strong proficiency with PrimeTime, IC Compiler II or Fusion Compiler, ICV, and RedHawk
• Solid scripting skills in Tcl and Python for flow automation

Preferred Qualifications

• Experience with UCIE or die-to-die interconnect standards

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, partnering closely with customers across various industries to power the next generation of innovation.