SOC Engineering, Staff Engineer (Physical Design) at Synopsys - ScoutJobs - The AI-curated global job board
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Synopsys
Posted 13 hours ago

SOC Engineering, Staff Engineer (Physical Design)

SynopsysSOC Engineering, Staff Engineer (Physical Design)

Perks & benefits

Medical InsurancePaid LeaveMobile Allowance

Requirements

Bachelor's, Master's, or Ph.D. in Electrical or Computer Engineering, 3 to 10+ years ASIC physical design experience, RTL-to-GDSII ownership, Experience with 7nm, 5nm, or 3nm nodes, Expertise in UCIe, HBM, or high-speed DDR, Proficiency in IC Compiler II, Fusion Compiler, or PrimeTime, Advanced scripting in Tcl, Python, or Shell

Skills

ASICPythonPhysical Design

About the role

Responsibilities

  • Own RTL-to-GDSII physical implementation for UCIe IP blocks, driving synthesis, floorplanning, power grid architecture, placement, clock tree synthesis, routing, and sign-off closure.
  • Close timing across multiple PVT corners and operating modes, optimizing for the latency and bandwidth demands of high-speed die-to-die interfaces.
  • Execute physical and electrical verification using Synopsys IC Validator, resolving DRC, LVS, ERC violations and mitigating electromigration, IR-drop, and signal integrity issues.
  • Design and validate bump and pad ring patterns specific to die-to-die architectures, coordinating with package teams on complex routing constraints.
  • Build and maintain automation scripts in Python, Tcl, and Perl to streamline back-end flows and eliminate bottlenecks.
  • Prepare and deliver tape-out packages including GDSII databases, foundry checklists, and design documentation.

Requirements

  • Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
  • 3 to 10+ years of hands-on ASIC physical design experience with proven RTL-to-GDSII ownership.
  • Experience with 7nm, 5nm, or 3nm semiconductor nodes.
  • Deep technical expertise in die-to-die interfaces such as UCIe, HBM, or high-speed DDR.
  • Strong proficiency with Synopsys physical design tools including IC Compiler II, Fusion Compiler, and PrimeTime.
  • Advanced scripting skills in Tcl, Python, or Shell for automating complex design flows.

Benefits

  • Comprehensive medical and healthcare plans.
  • Paid time away including ETO and FTO programs.
  • Family support including maternity/paternity leave and adoption assistance.
  • Employee Stock Purchase Plan (ESPP) with a 15% discount.
  • Competitive salaries and regional retirement plans.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, partnering closely with customers to maximize R&D productivity and power the next generation of innovation.

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SOC Engineering, Staff Engineer (Physical Design)

Synopsys · Da Nang

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