
Posted 6 days ago
SOC Engineering, Principal Engineer
SynopsysSOC Engineering, Principal Engineer
Perks & benefits
Medical InsurancePaid LeaveMobile Allowance
Requirements
Bachelor's or Master's in Electronics or Electrical Engineering, 12+ years experience in static timing analysis, Experience with 7nm, 5nm, or 3nm nodes, Proficiency in Synopsys EDA tools (PrimeTime, PrimePower, PrimeClosure, Tweaker), Scripting skills in Python, PERL, or TCL
Skills
Python
About the role
Responsibilities
- Independently own and drive signoff static timing analysis (STA) and timing closure for advanced process nodes (7nm, 5nm, and 3nm).
- Execute STA, power analysis, synthesis, and timing/power closure to meet stringent performance and power targets.
- Develop and validate timing constraints at both block-level and full SoC level.
- Collaborate with cross-functional global teams to resolve complex design challenges and ensure schedule adherence.
- Utilize and optimize Synopsys EDA tools including PrimePower, PT-PX, PrimeClosure, and Tweaker.
- Develop and maintain automation scripts in Python, PERL, or TCL to streamline design flows and improve efficiency.
- Contribute to the continuous improvement of STA flows and methodologies while mentoring junior engineers.
Requirements
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field.
- 12+ years of relevant experience in static timing analysis, specifically with advanced technology nodes (7nm, 5nm, or 3nm).
- Comprehensive hands-on experience in constraints development, validation, STA, power analysis, and timing/power ECO generation.
- Proficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, and Tweaker.
- Strong scripting and automation skills using Python, PERL, or TCL.
- Solid understanding of timing constraints, clock tree structures, and physical implementation impact.
Preferred Qualifications
- Working experience with Synopsys tools like Fusion Compiler, Design Compiler, Formality, and StarRC.
- Knowledge of synthesis, implementation, parasitic extraction, and formal verification.
- Experience with high-frequency and low-power design methodologies.
Benefits
- Comprehensive medical and healthcare plans.
- Paid time off including ETO and FTO programs.
- Family support including maternity/paternity leave and adoption assistance.
- Employee Stock Purchase Plan (ESPP) with a 15% discount.
- Competitive salary and regional retirement plans.
About the Company
Synopsys is a leader in chip design, verification, and IP integration. We drive the innovations that shape the way we live and connect, providing the technology central to the Era of Pervasive Intelligence.
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Synopsys · Bengaluru
