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Posted 14 hours ago
SI/PI Engineer
EtchedSI/PI Engineer
Perks & benefits
Medical InsuranceHealth InsuranceHousing AllowanceRelocation Allowance
Requirements
B.S. or M.S. in Electrical Engineering, 5+ years SI/PI experience, Proficiency in Cadence Sigrity or Ansys SIwave, Knowledge of transmission line theory, PDN modelling experience, Hands-on lab skills (VNA, TDR, BERT)
Skills
PythonPCB
About the role
About the Company
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.
Responsibilities
- Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet
- Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines
- Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements
- Execute power delivery network (PDN) design and analysis including target impedance profiling and IR-drop simulation
- Drive DFI and design rule checks for SI/PI compliance using Cadence Allegro / Sigrity or Ansys SIwave
- Collaborate with PCB design and ASIC teams to define and review design guidelines
- Support bring-up, debug signal quality issues, and document root-cause findings
- Develop and maintain simulation-to-hardware correlation databases
Requirements
- B.S. or M.S. in Electrical Engineering or a closely related discipline
- 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces)
- Proficiency with industry SI/PI EDA tools (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent)
- Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition
- Experience with PDN modelling, target impedance methodology, and DC IR analysis
- Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing
- Hands-on lab skills including VNA, TDR, BERT operation, and oscilloscope probing
Preferred Qualifications
- Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments
- Experience scripting automated SI/PI simulation flows using Python or MATLAB
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose
- Various wellness benefits covering fitness and mental health
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification
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Etched · San Jose
