Silicon Validation Team Lead (NPU SoC)

Responsibilities

• Lead NPU 1st Silicon Bring-up including NPU accelerator cores, CPU Subsystem, NoC, and Memory Subsystem (LPDDR/HBM)
• Establish systematic validation methodologies for Pre-silicon (Emulator, FPGA) and Post-silicon environments
• Perform system-level issue debugging at the HW/SW boundary using JTAG and Trace32
• Support performance validation and optimization of NPU data pipelines and memory bandwidth
• Develop test automation scripts and integrate with CI/CD environments

Requirements

• Experience in SoC, ASIC, or complex Silicon/System Validation
• Leadership experience in validation planning, roadmap management, and team mentoring
• Deep understanding of ARM Architecture, AMBA BUS (AXI, AHB), and SoC/computer architecture
• Proficiency in Embedded C/C++ and Rust for bare-metal hardware control
• Expertise in JTAG debugging and HW/SW co-debugging
• Strong problem-solving skills for complex system-level issues

Preferred Qualifications

• Experience with AI accelerators (NPU, TPU), GPUs, or complex multi-core SoC bring-up
• Experience with Pre-silicon environments such as Palladium, Zebu, or FPGA
• Knowledge of High-Speed Interface protocols (Ethernet, CXL, LPDDR, HBM)
• Understanding of Linux Kernel and Device Driver operations
• Experience with Python, Tcl, or Bash for validation automation

About the Company

FuriosaAI's Silicon Validation team is a core department that ensures NPU chips operate perfectly at the system level before and after tape-out, bridging the gap between design (RTL/DV) and software (FW/OS).