Silicon Design Engineer

Responsibilities

• Define and implement the RTL for new AMD chiplet interconnect IP
• Participate in RTL implementation for functional blocks of the IP
• Optimize RTL implementation in cooperation with Architecture and RTL teams
• Optimize physical implementation in cooperation with the Physical Design team
• Perform synthesis, equivalence checking, CDC analysis, and area/power optimizations
• Conduct Linting and Static Timing Analysis (STA)

Requirements

• MSEE or BSEE degree
• 6+ years of experience in digital ASIC design
• Strong expertise in RTL design
• Experience with digital front-end implementation
• Proficiency in English (verbal and written)

Preferred Qualifications

• Experience with digital front-end implementation, including micro-architecture definition
• Experience using state-of-the-art industry standard digital tools
• RTL design experience with multi-clock, high-frequency designs
• Basic understanding of high-speed I/O protocols such as PCIe or UCIe

About the Company

AMD is on a mission to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. We push the limits of innovation to solve the world’s most important challenges through a culture of collaboration and excellence.