Serdes PHY Analog Design Engineer

Responsibilities

• Design multiple analog building blocks including LDO, high-speed TX/RX (Equalizer, Sampler, PI, Deserializer, etc.), Bias, and Reference circuits
• Develop Analog and/or Digital PLLs for frequency synthesis and SerDes applications, including charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers
• Manage the full design cycle from schematic to post-layout verification, integration sign-off, and post-silicon bring-up
• Collaborate closely with RTL, Digital Design, Physical Design, Design Verification, and SoC verification teams to integrate the PHY
• Perform PLL loop dynamics analysis and jitter source modeling (RJ & DJ)

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of hardware engineering experience (or Master's with 3+ years, or PhD with 2+ years)
• Extensive expertise in analog circuit design
• Proven experience with LDO, high-speed TX/RX, and PLLs
• Proficiency with SPICE simulators, adexl, and Virtuoso
• Hands-on experience with post-silicon bring-up and debug
• Scripting skills in Shell, Perl, or Python for automating design and verification tasks

Preferred Qualifications

• Mixed-signal design experience
• Understanding of advanced FinFET process effects on design and layout
• Knowledge of peripheral PHY protocols such as USB, UFS, or PCIe

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.