Senior/Staff Digital Design Engineer

About the Company

OLIX is building the next generation of AI infrastructure. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode, utilizing rack-scale co-design of logic, data movement, packaging, optics, and interconnect to achieve a step change in system-level performance.

Responsibilities

• Architect, design, and implement high-throughput digital pipelines in advanced CMOS nodes
• Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent)
• Model algorithms and validate concepts in MATLAB/Simulink
• Own RTL development including synthesis, static-timing closure, formal, and constrained-random verification
• Analyze power, performance, and area (PPA) to achieve aggressive bandwidth-per-watt targets
• Collaborate with optical-hardware, mixed-signal, and software teams
• Mentor junior engineers and lead design reviews

Requirements

• 7+ years of hands-on digital design for high-performance ASICs or SoCs
• Experience with continuous real-time data stream processing
• Success closing timing on multi-hundred-MHz to multi-GHz clock domains
• Integration of high-speed IP (SerDes, HBM/DDR, PCIe, 100 GbE)
• Expertise with industry-standard EDA flows (RTL synthesis, CDC/RDC, STA, UPF/CPF)
• Demonstrated FPGA prototyping and hardware debug skills
• Proficiency in MATLAB/Simulink or Python/NumPy for algorithm modeling
• Solid grounding in digital signal-processing and computer architecture

Preferred Qualifications

• Tape-out experience at 22 nm or below
• Knowledge of coherent optical links or photonic-electronic co-design
• Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures
• Contributions to open-source RTL or verification frameworks