Senior/Staff Design for Test Engineer

About the Company

OLIX is building the next generation of AI infrastructure. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode, utilizing rack-scale co-design of logic, data movement, packaging, optics, and interconnect to drive a step change in system-level performance.

Responsibilities

• Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes
• Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST
• Partner with test engineering to develop and optimize ATE-compatible test patterns to achieve aggressive fault coverage
• Drive RTL development with a focus on DFT architecture and synthesis constraints
• Analyze and minimize the DFT impact on power, performance, and area (PPA)
• Collaborate with mixed-signal and software teams to define and optimize DFT interfaces and test modes
• Mentor junior engineers and lead DFT design reviews

Requirements

• 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs
• Proven success implementing advanced DFT features (Scan/ATPG, Boundary Scan, Memory BIST/Repair)
• Expertise with industry-standard EDA flows including scan insertion, ATPG, and pattern simulation
• Demonstrated proficiency with compression techniques, EDT, and JTAG/IEEE 1149.1/1687
• Proficiency in Python or Tcl scripting for DFT flow automation and pattern management
• Solid grounding in semiconductor device physics and fault models

Preferred Qualifications

• Tape-out experience at 22 nm or below
• Knowledge of high-speed SerDes or HBM/DDR DFT challenges
• Familiarity with AI/ML workloads or systolic arrays
• Contributions to open-source DFT tools or verification frameworks