Senior/Staff Analog Design Engineer - SerDes

About the Company

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode, utilizing rack-scale co-design of logic, data movement, packaging, optics and interconnect to enable a step change in system level performance.

Responsibilities

• Architect and design high-speed SerDes blocks including serializers, TX drivers, TIAs, CTLEs, CDRs, deserializers, and clock generation in advanced FinFET nodes
• Perform schematic and post-layout simulations including EM-IR and reliability simulations
• Run EM simulations for passives, package interconnects, and on-die routing
• Develop behavioral and Verilog-A models for system-level and mixed-signal verification
• Supervise mask designers and provide floorplan and layout guidelines
• Collaborate with optical, digital, and system teams on interfaces and link-level performance
• Support post-silicon bring-up, lab validation, and debug

Requirements

• MS or PhD in Electrical Engineering
• 10+ years of analog/mixed-signal IC design experience
• Hands-on SerDes experience at data rates of 25 Gbps or higher
• Solid understanding of high-speed signaling concepts such as jitter, noise, equalization, and signal integrity
• Expertise in advanced FinFET nodes and device physics
• Proficiency with Cadence Virtuoso and Spectre
• Experience with PVT, Monte Carlo, EM-IR, and reliability analysis
• Experience developing Verilog-A models
• Familiarity with post-silicon bring-up and lab measurement equipment

Benefits

• Competitive Salary
• Meaningful stock options
• Annual Living-Local Bonus for residents within 20 minutes of the office
• Employer-contributed retirement plans