Senior Yield Enhancement Engineer

Responsibilities

• Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns
• Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques
• Develop and execute FIB (Focused Ion Beam) edit plans for Silicon root cause validation
• Communicate with OSATs and Fab to drive production testing in HVM environments
• Understand DFT strategies including hierarchical scan chains, distributed BIST, and SRAM test methodologies
• Collaborate with DFT engineers, silicon architects, and designers to enhance testability and yield
• Refine test programs regarding di/dt behavior, voltage-frequency characterization, and thermal constraints
• Write Python scripts and work within UNIX environments for data analysis

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of hands-on experience in semiconductor test engineering, Failure Analysis (FA), or Yield Enhancement
• Experience with lab debug tools including Oscilloscopes, wafer probe stations, and probe cards
• Expertise in failure analysis (FA) including optical probing and physical inspection workflows
• Ability to read and understand Digital CMOS layouts, power grids, and SRAM arrays
• Experience with ATE test program debugging and yield improvement
• Proficiency in programming languages such as Python, C/C++, or Perl
• Working knowledge of git repositories and GitHub

Preferred Qualifications

• Experience developing fault isolation techniques using OBIRCH, IREM, or LADA optical techniques
• Experience with advanced test data analysis tools and machine learning for yield optimization
• Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects)
• Knowledge of chip defect profiles and mitigation strategies across manufacturing steps

About the Company

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, empowering machine learning users to effortlessly run large-scale ML applications.