Senior VLSI Design Engineer

Responsibilities

• Provide High Speed DDR IO solutions for next generation Memory in advanced CMOS technology nodes
• Design high Speed IO Blocks, Powerbus analysis, Jitter / High speed timing closure
• Work closely with Layout and verification teams
• Participate in technical discussions and reviews
• Propose innovative design solutions and methodologies for future generations

Requirements

• Bachelors/Masters degree in Electronics & Telecommunication or Electrical engineering (VLSI Design)
• Hands-on design knowledge in Digital custom, Analog & mixed signal design environments
• 4+ years of experience with IO circuit blocks for memory products (DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6)
• Familiarity with custom design methodology, Calibration, JTAG design, and high-speed IO circuits (DLL, Rx, Tx, clocking)
• Knowledge of high-speed layout guidelines and analog layout techniques
• Proficiency with spice tools such as finesim and hspice

Preferred Qualifications

• NAND Flash Design knowledge
• Familiarity with package, board, Power integrity, or signal integrity constraints
• Automation and scripting knowledge