Senior Verification Engineer

Responsibilities

• Write verification specifications and test plans for next-generation DDR and HBM memory interface IP
• Design and build SystemVerilog testbenches and UVM environments for complex mixed-signal ASIC designs
• Develop and execute test cases targeting protocol compliance, signal integrity, and power-aware verification
• Create and maintain behavioral models in Verilog and SystemVerilog to enable early verification
• Drive coverage closure using functional, code, and assertion-based metrics
• Debug failures across digital and mixed-signal domains, working closely with design engineers to root-cause issues

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of hands-on verification experience in ASIC or mixed-signal design environments
• Deep expertise in SystemVerilog and UVM methodology
• Strong understanding of Verilog for RTL analysis and behavioral modeling
• Proficiency in scripting languages such as Python, Perl, or Tcl for automation
• Experience working in Unix/Linux environments and using industry-standard EDA tools

Preferred Qualifications

• Knowledge of high-speed interface protocols such as DDR, HBM, or DFI
• Experience with formal verification tools

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.