Senior Verification Engineer

Responsibilities

• Define and execute comprehensive verification plans for digital IPs
• Develop and implement verification testbenches, including drivers, monitors, and scoreboards
• Develop directed and constrained-random stimulus and functional coverage models
• Maintain SystemVerilog assertions (SVA) and apply formal verification methodologies
• Perform deep debugging, failure reproduction, and root-cause analysis
• Drive a “zero-defect” mindset and provide technical leadership to the verification team
• Mentor and grow junior engineers within the team
• Partner with global SoC and IP teams to drive best practices and productivity improvements

Requirements

• BSEE with 5+ years of semiconductor industry experience, MSEE with 3+ years, or PhD with 1+ years
• Strong expertise in Verilog and SystemVerilog
• Extensive experience with OVM/UVM and class-based verification methodologies
• Proficiency in scripting languages such as Python or Perl in a UNIX/Linux environment
• Knowledge of industry protocols such as DDR, PCIe, or AMBA (CHI, ACE, AXI)

Preferred Qualifications

• Experience with formal verification methodologies
• Experience leveraging AI/LLM-based approaches to improve engineering efficiency
• Knowledge of low-power verification using CPF/UPF
• Experience with FPGA, emulation, or prototyping platforms (e.g., HAPS, Palladium, Zebu)
• Familiarity with functional and code coverage methodologies

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.