Senior Technologist, Mask Design Engineering

Responsibilities

• Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed-Signal domains.
• Oversee DRC, LVS, parasitic extraction, and sign-off flows to ensure design integrity and first-pass silicon success.
• Architect full-chip power distribution networks and floorplans to optimize electrical performance and minimize die size.
• Collaborate with Design Engineering, Integration, and Process Technology teams globally to resolve design issues and align methodologies.
• Define and enhance layout methodologies, automation flows, and best practices to improve productivity and design quality.
• Provide technical direction and mentorship to senior layout engineers and conduct critical block reviews.

Requirements

• 22+ years of full-chip custom IC layout experience across analog, digital, and mixed-signal designs.
• Expert proficiency in DRC/LVS, parasitic extraction, EM/IR analysis, and sign-off verification using industry-standard tools.
• Proven ability to architect efficient floorplans and optimize placement using correct-by-construction approaches.
• Strong track record of collaborating with multi-site, cross-disciplinary teams and leading technical groups.
• Excellent communication skills and a proactive approach to methodology development and automation.

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world.