Senior Staff SOC Engineer (Physical Design)

Responsibilities

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA)
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure
• Collaborate with cross-functional global teams to resolve complex design challenges
• Utilize and optimize Synopsys EDA tools including Design Compiler, IC Compiler II, and PrimeTime
• Develop and maintain automation scripts in Python, PERL, or TCL to streamline design flows
• Contribute to design methodologies and mentor junior engineers

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field
• 5+ years of experience in physical design with advanced technology nodes (7nm/5nm/3nm)
• Hands-on experience with RTL2GDSII flows, synthesis, P&R, CTS, STA, EMIR, and physical verification
• Proficiency with Synopsys EDA tools (Design Compiler, IC Compiler II, PrimeTime)
• Strong scripting skills in Python, PERL, or TCL
• Solid understanding of timing constraints, timing closure, and floor-planning
• Experience with high-frequency and low-power design methodologies

Preferred Qualifications

• Experience in both block-level and full-chip floor-planning
• Ability to navigate aggressive timing schedules
• Proven track record of successful tape-outs

Benefits

• Comprehensive medical and healthcare plans
• ETO and FTO programs
• Maternity and paternity leave
• ESPP with 15% discount
• Regional retirement plans