Senior Staff Signal Integrity Engineer

Responsibilities

• Drive the SI/PI strategy for next-generation AI accelerators, focusing on high-speed interfaces like PCIe Gen6/7, CXL, and LPDDR5
• Lead modeling and analysis of complex multi-chip packages, including interposer routing and die-to-die link budgeting
• Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements
• Perform comprehensive channel simulations using IBIS-AMI models to define jitter, crosstalk, and loss budgets
• Lead lab validation by correlating simulation results with VNA, TDR, and high-speed oscilloscope measurements
• Translate simulation findings into actionable physical layout constraints for the PCB Design team
• Provide technical mentorship and guidance on SI/PI best practices to hardware and layout engineers

Requirements

• MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity
• 12+ years of experience in SI/PI design for high-performance networking, GPUs, or server platforms
• Expert proficiency in SI tools such as Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor
• Expert proficiency in PI tools such as Ansys SIwave, Cadence PowerSI, or CST
• Proven track record with 112G SerDes and high-speed memory architectures
• Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes

Preferred Qualifications

• Knowledge of PCB Material Science including glass weave effects and skin effect loss
• Experience with Python or MATLAB for automating sweep analysis and post-processing datasets
• Familiarity with OCP (Open Compute Project) hardware specifications for AI modules

About the Company

d-Matrix is focused on unleashing the potential of generative AI to power the transformation of technology through software and hardware innovation.