Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to develop consolidated timing modes and constraints for synthesis, PnR, and chip timing sign-off flows.
• Own front-end implementation tasks including Synthesis, UPF development, Logical Equivalence Checks (LEC), and Functional ECOs.
• Analyze tradeoffs between power, performance, and area (PPA) goals to drive chip implementation.
• Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
• Automate front-end flows and processes using scripting languages such as Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to Physical Design.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 5-10 years of professional experience, OR a Master’s/PhD with 3-5 years of experience.
• Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Hands-on experience with synthesis and STA methodologies.
• Proficiency in synthesis tools, STA tools, and scripting languages (Tcl, Perl, or Python).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Experience with functional ECOs and UPF development/validation.

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, AI, and carrier architectures, our innovative technology is enabling new possibilities and fueling the transformative potential of tomorrow.