Senior Staff ASIC Design Engineer

Responsibilities

• Help develop the design and implementation/ integration of SoCs
• Perform micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks
• Support prototyping, test program development, chip validation, and chip life until production maturity
• Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams

Requirements

• 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization
• Proficiency in writing clear, implementable micro-architecture specifications
• Expertise in writing efficient RTL code in Verilog and SoC integration
• Strong understanding of assertions, coverage analysis, RTL synthesis, and timing closure
• Experience with interface protocols such as PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, or SPI
• Experience in design bring up and debug on FPGA based emulation platforms like HAPS or Veloce
• Fluency with scripting languages like Perl or Python
• Proven track record of completing at least one full tape-out cycle

Preferred Qualifications

• Silicon bring-up and debug experience
• Experience with repository management tools like Bitbucket or Jenkins
• Experience with bug tracking tools like JIRA

About the Company

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.